Microdevices, such as integrated circuits, are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating integrated circuit devices typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of integrated circuit being designed, its complexity, the design team, and the integrated circuit fabricator or foundry that will manufacture the integrated circuit. Typically, software and hardware “tools” will verify a design at various stages of the design flow by running software simulators and/or hardware emulators, and errors in the design are corrected.
Several steps are common to most design flows. Initially, the specification for the new integrated circuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit is described in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). The logical of the circuit is then analyzed, to confirm that the logic incorporated into the design will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”
After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices (such as transistors, resistors, and capacitors) that will be used in the circuit, along with their interconnections. This logical generally corresponds to the level of representation displayed in conventional circuit diagrams. Preliminary timing estimates for portions of the circuit may be made at this stage, using an assumed characteristic speed for each device. In addition, the relationships between the electronic devices are analyzed, to confirm that the circuit described by the device design will correctly perform the functions desired for the circuit. This analysis is sometimes referred to as “formal verification.”
Once the relationships between circuit devices have been established, the design is again transformed, this time into a physical design that describes specific geometric elements. This type of design often is referred to as a “layout” design. The geometric elements define the shapes that will be created in various materials to actually manufacture the circuit device components (e.g., contacts, gates, etc.) making up the circuit. While the geometric elements are typically polygons, other shapes, such as circular and elliptical shapes, also may be employed. These geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Geometric elements also are added to form the connection lines that will interconnect these circuit devices. Layout tools, such as Mentor Graphics' IC Station or Cadence's Virtuoso, are commonly used for both of these tasks.
With a layout design, each physical layer of the integrated circuit will have a corresponding layer representation, and the geometric elements described in a layer representation will define the relative locations of the circuit device components that will make up a circuit device. Thus, the geometric elements in the representation of an implant layer will define the regions where doping will occur, while the geometric elements in the representation of a metal layer will define the locations in a metal layer where conductive wires used will be formed to connect the circuit devices. Typically, a designer will perform a number of analyses on the layout design. For example, the layout design may be analyzed to confirm that it accurately represents the circuit devices and their relationships described in the device design. The layout design also may be analyzed to confirm that it complies with various design requirements, such as minimum spacings between geometric elements. Still further, it may be modified to include the use of redundant or other compensatory geometric elements intended to counteract limitations in the manufacturing process, etc. After the layout design has been finalized, then it is converted into a format that can be employed by a mask or reticle writing tool to create a mask or reticle for use in a photolithographic manufacturing process.
Some of these physical verification processes are based on one simple concept: certain geometric shapes cannot be successfully manufactured with a given manufacturing process. Historically, a chip manufacturer would have a failure analysis (FA) team identify these configurations, generate a geometric representation of the problematic features in those configurations, and then derive an engineering specification for excluding those problematic features from new designs. This type of engineering specification typically would be interpreted and formulated as a design rule. The derived design rule would then be added to the rule decks for use during a physical verification process.
The above design rule checking (DRC) process worked well when most problem features could be defined with simple one-dimensional checks (length, width, distance, etc.). However, as the microdevice manufacturing industry reached the advanced nodes of the nanometer era, shapes became more complex, and the interactions between design features became multi-dimensional. Some configurations are now so complex they cannot be accurately described with existing scripting languages, inevitably resulting in checking errors. Additionally, significant time and expertise must be spent in the attempt to reach congruence between the original intent of the design rule and its implementation in a DRC process. Moreover, as advanced nodes are being implemented, problematic configurations or patterns are now being identified by designers using lithography and optical process simulations well before silicon production and the creation of design rules. These designers also need the ability to capture and transfer problematic configurations to other designers.
Using the original visual representation of a configuration rather than the abstraction and derivation can dramatically simplify the process of defining and transferring information about a problematic configuration in a layout design to a designer. Pattern matching can also reduce runtimes for simulation by targeting specific configurations within a design, allowing a designer to focus simulation resources on those configurations. Therefore, pattern matching (or pattern detection) is becoming a widely used approach in today's semiconductor industry. Accordingly, the industry is continuously seeking techniques for improving the efficiency of or reducing the process time of pattern matching.